LAPIC model is different on x86 and ia64, so make irq-pending

notification arch specific.

Signed-off-by Kevin Tian <Kevin.tian@intel.com>
Signed-off-by Yunhong Jiang <Yunhong.jiang@intel.com>

diff --git a/xen/arch/ia64/vmx/vlsapic.c b/xen/arch/ia64/vmx/vlsapic.c
index 3b378d07b46528c6df3afe8b4ba55dc06ffb8124..032d3633b176b3874fbfafac456d2e46189e8d29 100644 (file)
--- a/xen/arch/ia64/vmx/vlsapic.c
+++ b/xen/arch/ia64/vmx/vlsapic.c
@@ -476,19 +476,20 @@ static int irq_masked(VCPU *vcpu, int h_pending, int h_inservice)
  * May come from virtualization fault or
  * nested host interrupt.
  */
-void vmx_vcpu_pend_interrupt(VCPU *vcpu, UINT64 vector)
+int vmx_vcpu_pend_interrupt(VCPU *vcpu, uint8_t vector)
 {
     uint64_t    spsr;
+    int ret;
 
     if (vector & ~0xff) {
         DPRINTK("vmx_vcpu_pend_interrupt: bad vector\n");
         return;
     }
     local_irq_save(spsr);
-    VCPU(vcpu,irr[vector>>6]) |= 1UL<<(vector&63);
-    //vlapic_update_shared_irr(vcpu);
+    ret = test_and_set_bit(vector, &VCPU(vcpu, irr[0]));
     local_irq_restore(spsr);
     vcpu->arch.irq_new_pending = 1;
+    return ret;
 }
 
 /*
@@ -505,7 +506,6 @@ void vmx_vcpu_pend_batch_interrupt(VCPU *vcpu, UINT64 *pend_irr)
     for (i=0 ; i<4; i++ ) {
         VCPU(vcpu,irr[i]) |= pend_irr[i];
     }
-    //vlapic_update_shared_irr(vcpu);
     local_irq_restore(spsr);
     vcpu->arch.irq_new_pending = 1;
 }
@@ -592,7 +592,6 @@ uint64_t guest_read_vivr(VCPU *vcpu)
     VLSAPIC_INSVC(vcpu,vec>>6) |= (1UL <<(vec&63));
     VCPU(vcpu, irr[vec>>6]) &= ~(1UL <<(vec&63));
     update_vhpi(vcpu, NULL_VECTOR);     // clear VHPI till EOI or IRR write
-    //vlapic_update_shared_irr(vcpu);
     local_irq_restore(spsr);
     return (uint64_t)vec;
 }

diff --git a/xen/arch/x86/dm/vmx_vioapic.c b/xen/arch/x86/dm/vmx_vioapic.c
index b97a9b4bc2b29514460846115f3967ade4c8466a..769eb59f228bf9dc8355e031cf1d4aa60b067a9c 100644 (file)
--- a/xen/arch/x86/dm/vmx_vioapic.c
+++ b/xen/arch/x86/dm/vmx_vioapic.c
@@ -306,14 +306,8 @@ static int ioapic_inj_irq(vmx_vioapic_t *s,
     switch (delivery_mode) {
     case VLAPIC_DELIV_MODE_FIXED:
     case VLAPIC_DELIV_MODE_LPRI:
-        if (test_and_set_bit(vector, &VLAPIC_IRR(target)) && trig_mode == 1) {
-            /* the level interrupt should not happen before it is cleard */
+        if (vlapic_set_irq(target, vector, trig_mode) && (trig_mode == 1))
             printk("<ioapic_inj_irq> level interrupt happen before cleard\n");
-        }
-#ifndef __ia64__
-        if (trig_mode)
-            test_and_set_bit(vector, &target->tmr[0]);
-#endif
         result = 1;
         break;
     default:

diff --git a/xen/include/asm-ia64/vmx_platform.h b/xen/include/asm-ia64/vmx_platform.h
index e36188898adb5d0c33e68ea115fb8f29432f455b..f72dfb9068779419b879d081a36cdb44ec85c1d1 100644 (file)
--- a/xen/include/asm-ia64/vmx_platform.h
+++ b/xen/include/asm-ia64/vmx_platform.h
@@ -55,6 +55,12 @@ extern uint64_t dummy_tmr[];
 #define VLAPIC_ID(l) (uint16_t)(VCPU((l)->vcpu, lid) >> 16)
 #define VLAPIC_IRR(l) VCPU((l)->vcpu, irr[0])
 
+extern int vmx_vcpu_pend_interrupt(struct vcpu *vcpu, uint8_t vector);
+static inline int vlapic_set_irq(struct vlapic *t, uint8_t vec, uint8_t trig)
+{
+    return vmx_vcpu_pend_interrupt(t->vcpu, vec);
+}
+
 /* As long as we register vlsapic to ioapic controller, it's said enabled */
 #define vlapic_enabled(l) 1
 #define vmx_apic_support(d) 1

diff --git a/xen/include/asm-ia64/vmx_vcpu.h b/xen/include/asm-ia64/vmx_vcpu.h
index 4f9017552515003453dfe42c7748e8eaaca071cc..2367d00590f178a53fd0b63ba9567db62a287c00 100644 (file)
--- a/xen/include/asm-ia64/vmx_vcpu.h
+++ b/xen/include/asm-ia64/vmx_vcpu.h
@@ -112,7 +112,7 @@ extern int vmx_check_pending_irq(VCPU *vcpu);
 extern void guest_write_eoi(VCPU *vcpu);
 extern uint64_t guest_read_vivr(VCPU *vcpu);
 extern void vmx_inject_vhpi(VCPU *vcpu, u8 vec);
-extern void vmx_vcpu_pend_interrupt(VCPU *vcpu, UINT64 vector);
+extern int vmx_vcpu_pend_interrupt(VCPU *vcpu, uint8_t vector);
 extern struct virutal_platform_def *vmx_vcpu_get_plat(VCPU *vcpu);
 extern void memread_p(VCPU *vcpu, u64 *src, u64 *dest, size_t s);
 extern void memread_v(VCPU *vcpu, thash_data_t *vtlb, u64 *src, u64 *dest, size_t s);
@@ -474,4 +474,7 @@ vmx_vrrtomrr(VCPU *v, unsigned long val)
 #endif 
 
 }
+
+#define check_work_pending(v)  \
+    (event_pending((v)) || ((v)->arch.irq_new_pending))
 #endif

diff --git a/xen/include/asm-x86/vmx_vlapic.h b/xen/include/asm-x86/vmx_vlapic.h
index 991a6f36c168ec2a82d0f28d36ec8fd02a38400e..ef33d42dab3b346a2e0deb6059e681508bcd13b1 100644 (file)
--- a/xen/include/asm-x86/vmx_vlapic.h
+++ b/xen/include/asm-x86/vmx_vlapic.h
@@ -202,6 +202,18 @@ struct vlapic
     struct domain      *domain;
 };
 
+static inline int vlapic_set_irq(struct vlapic *t, uint8_t vec, uint8_t trig)
+{
+    int ret;
+
+    ret = test_and_set_bit(vec, &t->irr[0]);
+    if (trig)
+       test_and_set_bit(vec, &t->tmr[0]);
+
+    /* We may need to wake up target vcpu, besides set pending bit here */
+    return ret;
+}
+
 static inline int  vlapic_timer_active(struct vlapic *vlapic)
 {
     return  active_ac_timer(&(vlapic->vlapic_timer));